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12/2008 - Present Director of Electronics team developing ASICs and TFT-backplane control circuits for MEMS-based, high-quality, low-power, small form factor displays.
12/2007 - 12/2008 Manager of ASIC Development for the development of control ASICs used in low-power, high quality displays for handheld devices.
6/2004 - 11/2007 Engineering Manager of the 8 person Network Systems Group east-coast chip engineering team. Managed design, verification, and debug work on all FPGAs in all versions of the Sun Secure Application Switch. Managed architecture, design, and verification of programmable chips used for power management and hot-plug control of the processor blades in the Sun Blade 8000 Modular System. Coordinated and managed development of the control plane chips used in several Network Express Modules for the SB8000.
1/2004 - 6/2004 Senior Staff Engineer in the Network Systems Group, continuing the work from Nauticus on the Sun Secure Application Switch family. Produced cost-reduced version of the Stream Memory Manager used in the Sun Secure Application Switch N1000 Series. Worked on architectural definition of next-generation switch.
1/2001 - 1/2004 Principal Design Engineer in a networking startup creating powerful new infrastructure products to deliver the next generation internet. Designed a 64GB Stream Memory Manager FPGA written in Verilog. Responsible for architectural definition, implementation, and functional and performance testing. Worked closely with System Architect and other chip designers to define the Data Flow Architecture used for communications between the chips and the software running on Network Processors.
4/99 - 12/2000 Hardware Manager of a 25 person ASIC design team working on three to four concurrent projects. Responsible for performance reviews, scheduling, resource allocation, long-term resource planning, and daily management of the team. >Primary Hardware Manager for all of the Radeon graphics functionality, which was developed across three sites. Responsibile for direct management of local design team, coordination of development schedules with the teams at other sites, resolution of multiple-customer issues, and communication between marketing, architecture, senior management, and the design teams.
4/98 - 3/99 Hardware Project Technical Lead of the team developing the Radeon. Gave technical direction to a team of 30 hardware designers at two sites. Developed and documented design methodologies and processes, and tested new tools and flows. Coordinated and scheduled development of documention, HDL design, and synthesis. Directly interfaced with the layout team. Mentored new hires. Refined a data manipulation mechanism and worked with an attorney on several patent applications.
3/97 - 3/98 Senior Hardware Designer in a team developing high performance graphics accelerators for the PC and Mac markets. Designed and implemented deeply pipelined multi-port Pixel Cache for Rage128. Coordinated work of designers in Toronto. Generated documentation and refined patent applications (two pending). Synthesized portions of the design using Synopsys, and tested the design using a QuickTurn Hardware Emulator.
4/96 - 3/97 Senior ASIC Designer in a small team implementing the PM35/ PM36 JPEG codec in standard-cell silicon with VHDL and datapath methodologies. Designed, implemented, tested, synthesized, and optimized three of the the five primary functional blocks in a very high speed semicustom JPEG endec chip.
10/94 - 3/96 Project Leader of a 22 person team designing and implementing the disk controller chip for Quantum's high-end SCSI disk, the Atlas II. Defined architectural requirements and implementation guidelines and standards. Performed several feature, cost, and risk analyses to develop a schedule and resource allocation. Also designed and implemented a major section of the chip. As a member of the Digital Chip team's 5 person senior staff, I had supervisory, hiring, and contracting responsibilities. I also managed a suite of GNU tools and assisted coworkers with system related problems.
1/94 - 10/94 Project Leader of a six person team implementing a very high speed PRML detector chip intended for the read-chain of Digital's next generation of disks. Evaluated and recommended ECAD tools. Narrowed the silicon vendor selection process, culminating in the preparation of a detailed request for quote. Worked with Architecture team to generate a specification of an implementable chip meeting product scheduling constraints. Generated schedules and resource allocations. Interfaced to PCB, software engineering, and reliability groups, as well as design teams of 4 other custom chips. Identified weaknesses in the development process and promoted approaches to minimize technical and schedule risk. Performed design and test bench development until the project was canceled due to Quantum's acquisition of Digital's storage division.
3/93 - 1/94 Contributing Member of three person team working on a disk controller chip that interfaced to the AT bus. Became acquainted with the ATA Specification. Became familiar with and identified several bugs in the existing design, and fixed many of them. Wrote tests and specifications for the logic until the project was cancelled.
2/92 - 3/93 Project Leader of a five person team implementing Digital's last generation of disk controller chip. Identified customers and requirements. Wrote specifications and held reviews to resolve conflicting requirements. Performed in-depth cost/benefit analysis of requested features. Generated and monitored project schedules. Allocated and coordinated the work of all designers. Designed, implemented, and tested several improvements and new features in the data path. Managed new-functional and regression testing. Oversaw the fault grade vector generation. Generated dynamic burnin connection lists and vectors for two different sets of burnin hardware. Performed Failure Analysis for burnin failures. Also configured, managed, and maintained an 8 node VMS VAXCluster.
5/90 - 2/92 Lead Engineer of five person team which developed Digital's first banded hard disk controller chip. Developed a framework for managing concurrent design by multiple designers. Identified required and optional improvements over previous generation of chip, held requirements reviews, rewrote specification. Worked closely with design teams of three other custom chips to insure compatibility. Worked on banded format and associated patent application. Redesigned, implemented, tested, and integrated the data path to support a custom multi-frequency data separator chip. Performed post layout regression testing and verification.
1/89 - 4/90 Contributing Member of four person team which converted and improved a custom hard disk controller chip from NMOS to a CMOS gate array. Became familiar with existing logic in the primary data path, rearchitected it, wrote a specification for the new logic, held reviews, redesigned, tested, and integrated the logic. Wrote behavioral models and translation tools for testing. Invented a new way to do pattern matching and initiated patent application process.
6/87 - 12/88 Contributing Member of three person team which developed a standard cell ASIC interface to Digital's proprietary SCSI-like bus (DSSI). Identified design requirements, partitioned design into functional blocks, designed, implemented, and tested two of the six functional blocks. Generated all of the fault grade and dynamic burnin vectors for manufacturing support. Wrote format conversion tools for vector translation. Wrote a small amount of MC68000 assembler and C code and designed special interface logic to test engineering prototypes. Wrote patent disclosure for new technology used in the chip, presented data to internal patent committee, and worked with patent attorney to write patent application.
1988 - 1990 Worcester Polytechnic Institute Took graduate classes in digital systems design and signal processing.
1987 - 1994 Digital Equipment Corporation Education and Training Took classes on Digital Systems Design, Error Correcting Codes, Coding Theory, C++, etc.
1983 - 1987 Massachusetts Institute of Technology Received Bachelor of Science in Electrical Engineering.
| 26 January 1993 | 5,182,752 | Method and apparatus for transferring data between a data bus and a data storage element. |
| 11 January 1994 | 5,278,703 | Embedded servo banded format for magnetic disks for use with a data processing system. |
| 12 November 1996 | 5,574,448 | Method and apparatus for encoding data with variable block lengths |
| 9 January 2001 | 6,173,367 | Method and apparatus for accessing graphics cache memory |
| 30 January 2001 | 6,182,196 | Method and apparatus for arbitrating access requests to a memory |
| 21 August 2001 | 6,279,080 | Method and apparatus for association of memory locations with a cache location having a flush buffer |
| 25 September 2001 | 6,295,581 | Method and apparatus for assuring cache coherency |
| 5 November 2002 | 6,476,811 | Method and apparatus for compressing parameter values for pixels in a display frame |
| 2 December 2003 | 6,658,531 | Method and apparatus for accessing graphics cache Memory |
| 27 June 2006 | 7,069,397 | Stream based memory manager with function specific hardware logic for accessing data as a stream in memory |
Last Modified Thursday, 23-Jul-2009 08:04:30 EDT